1. Field of the Invention
The present invention relates generally to waveform generators, and particularly to waveform generators employed in DDS applications.
2. Technical Background
Direct digital synthesis is a technique that is currently used in a variety of applications to generate RF waveforms. Briefly stated, a direct digital synthesizer stores the amplitudes of a single cycle of a waveform in a digital format and reads these digital values as a function of the advancing phase to generate a digital waveform. The digital waveform is directed into a digital-to-analog converter to generate an analog waveform corresponding to the stored values. A more detailed explanation is provided below.
FIG. 1 is a block diagram of a DDS implementation 100 that may be employed in a waveform generator, local oscillator, or other such applications. A pulse control circuit provides pulse frequency data to the frequency command register 102. The frequency command register 102 is coupled in series to a phase accumulator 104. The frequency command register 102 includes registers that store control bits that function as a means for “tuning” the output signal in accordance with predetermined signal transmission characteristics such as modulation format, frequency, bandwidth, pulse width, etc. Phase accumulator 104 is typically implemented as a free-running counter that continuously increments with each system clock signal applied thereto. The counter 104 is coupled to the address lines of phase-to-amplitude converter 106. Converter 106 is typically implemented as a look-up table (LUT). LUT 106 stores data corresponding to the amplitude of the cosine wave as a function of advancing phase. Therefore, as each memory location is read, a digital word is retrieved. The sequence of digital words read from LUT 212 corresponds to the advancing phase of a cosine wave (i.e., over the interval of 0-2π radians, i.e., 0°-360°. In many applications, the amplitude data is directed into the DAC to obtain an analog waveform. However, the digital-to-analog converter (DAC) introduces a sin(x)/x roll off distortion in the frequency domain. In conventional systems, this distortion is corrected by the inclusion of digital filter 108. This drawback is described in greater detail in FIGS. 3-5.
Referring to FIG. 2, a diagrammatic depiction of a sampled waveform output of a DAC is shown. The DAC output waveform is generated by converting the digital amplitude value provided by converter 106 into a discrete voltage value. The voltage is held for a period of time. Accordingly, the DAC outputs a “sampled” cosine waveform that exhibits discrete amplitude steps. For example, if the DAC operates at 100 MHz, waveform component 202 may be viewed as a rectangular function having a 10 nanosecond (nsec.) period and a 0.2 V amplitude. When the phase angle is at 90°, the amplitude has increased to approximately one (1.0) volt.
As those of ordinary skill in the art will appreciate, the Fourier transform of a rectangular function in the time domain is a Sinc function, i.e., sin (x)/x, in the frequency domain. FIG. 3 is a diagrammatic depiction of the frequency response of the sampled waveform shown in FIG. 2. Again, the example provided is based on a DAC having a 100 MHz sampling rate. Note that frequency response 30 experiences a severe sin (x)/x “roll-off” as the DDS frequency approaches 50 MHz. At lower frequencies, the roll-off is negligible. At point 300, the frequency is approximately 40 MHz. At point 302, the frequency is set at 50 MHz and the output is in the first null of the sin (x)/x function. To mitigate the effects of the sin (x)/x roll-off, DDS architectures typically employ a digital filter 108 that applies the inverse of sin (x)/x. FIG. 4 is a diagram of the frequency response of the inverse sin (x)/x digital filter 108 shown in FIG. 1. The object of the filter, or course, is to flatten the overall frequency response of the DDS.
However, conventional digital filter implementations have drawbacks. As those of ordinary skill in the art will understand, digital filters of the type described above are often implemented using a finite impulse response (FIR) filter. The FIR filter is used to solve a difference equation wherein the output equals the sum of a series of terms. Each term is a version of the input signal multiplied by a predetermined coefficient. If for example, the input sample is a 16-bit word and there are 19 taps in the delay chain, the filter will require 19 multiplications and additions per DAC sample. If the DAC operates at the 100 MHz sampling rate used in the previous examples, the calculations must be performed within the 10 nsec period. Accordingly, the FIR filter cannot be implemented in software and must be implemented using dedicated hardware in this example.
In the hardware implementation, the delay chain is implemented using one D-type flip-flop for each bit in the sample. In the above example, therefore, the delay 16 D-type flip-flops are required for each stage of the 19-tap filter. Further, each stage requires a multiplier and additional registers to store the tap coefficient. Finally, the products of each of the stages are added together. In one implementation, the hardware logic required to build the inverse sin (x)/x filter consumes 0.85 W. For a 3 W system, this amounts to a 30% increase in the power consumption. Of course, the increase in power consumption directly translates into an increase in the amount of heat that the system must dissipate.
Another drawback relates to the delays associated with the filter itself. In a 19-tap filter, there are, at minimum, 19 cycles of delay. If the system clock is running at 300 MHz, i.e., a 3.3 nsec clock period, the minimum delay will be almost 63 nsec.
What is needed, therefore, is an equalizer that minimizes both delay and power consumption. Further, an equalization filter having an adjustable filter response is needed. For example, an adjustable filter that is dynamically reconfigurable to pre-distort a generated waveform to account for amplitude variations in downstream RF processing would be quite desirable.